1. Field of the Invention
The present invention relates to a semiconductor storage device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor storage device employing SRAM (Static Random Access Memory) memory cells and a manufacturing method of the semiconductor storage device.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory) are each widely used as a typical semiconductor storage device.
Some types of SRAM memory cells are known. For example, as one of the memory-cell types, the SRAM memory cell employs at least a total of six MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The six MOSFETS are two PMOS (P-channel Metal-Oxide-Semiconductor) transistors and four NMOS (N-channel Metal-Oxide-Semiconductor) transistors.
In comparison with a semiconductor storage device requiring components such as a capacitor used specially as a memory in addition to transistors like DRAMs, the SRAM offers merits such as a process compatible with the pure logic process, simple peripheral circuits and a high access speed. In comparison with the DRAM requiring an operation to refresh data stored in the DRAM, the peripheral circuits of the SRAM can be made simple because an operation to refresh data stored in the SRAM is not required. Because of these merits, the SRAM is widely used as a semiconductor storage device which is required to have a high access speed and simple peripheral circuits but needs to have only a relatively small storage capacity. Examples of the semiconductor storage device are a cache memory and a memory employed in a portable terminal.
FIG. 9A is a circuit diagram showing an equivalent circuit of an SRAM memory cell employing six MOSFETs. Typically, the six MOSFETS are two PMOS transistors and four NMOS transistors. In the equivalent circuit, the two PMOS transistors are a first load transistor LTr1 and a second load transistor LTr2. On the other hand, the four NMOS transistors are a first driver transistor DTr1, a second driver transistor DTr2, a first transfer transistor TTr1 and a second transfer transistor TTr2.
The drains of the first load transistor LTr1 and the first driver transistor DTr1 are connected to a first storage node ND whereas the gates of the first load transistor LTr1 and the first driver transistor DTr1 are connected to a second storage node ND/. The source of the first load transistor LTr1 is connected to a power-supply voltage Vc whereas the source of the first driver transistor DTr1 is connected to a reference electric potential Vs. In this configuration, the first load transistor LTr1 and the first driver transistor DTr1 form a first CMOS inverter employing the second storage node ND/ as the input terminal and the first storage node ND as the output terminal.
On the other hand, the drains of the second load transistor LTr2 and the second driver transistor DTr2 are connected to the second storage node ND/ whereas the gates of the second load transistor LTr2 and the second driver transistor DTr2 are connected to the first storage node ND. The source of the second load transistor LTr2 is connected to the power-supply voltage Vc whereas the source of the second driver transistor DTr2 is connected to the reference electric potential Vs. In this configuration, the second load transistor LTr2 and the second driver transistor DTr2 form a second CMOS inverter employing the first storage node ND as the input and the second storage node ND/ as the output.
Thus, the input of the first CMOS inverter composed of the first load transistor LTr1 and the first driver transistor DTr1 as described above is connected to the output of the second CMOS inverter composed of the second load transistor LTr2 and the second driver transistor DTr2 as described above whereas the output of the first CMOS inverter is connected to the input of the second CMOS inverter to form a ring functioning as a storage circuit.
The gate, drain and source of the first transfer transistor TTr1 are connected to a word line WL, a bit line BL and the first storage node ND respectively. By the same token, the gate, drain and source of the second transfer transistor TTr2 are connected to the word line WL, a complementary-bit line BL/ and the second storage node ND/ respectively.
FIG. 9B is a top view showing a layout of the SRAM memory cell MC having an equivalent circuit shown in the circuit diagram of FIG. 9A. In recent years, the area of a memory cell MC is contracted in an attempt to increase the density of a semiconductor storage device. In many SRAMs of 90 nm and 65 nm generations, a point-symmetrical memory cell like the one shown in the top view of FIG. 9B is used.
As shown in the top view of FIG. 9B, a first P-type semiconductor area P1, a second P-type semiconductor area P2, a first N-type semiconductor area N1 and a second N-type semiconductor area N2 are isolated from each other by a device isolating insulation film I. Each of the first P-type semiconductor area P1, the second P-type semiconductor area P2, the first N-type semiconductor area N1 and the second N-type semiconductor area N2 is typically configured as a well formed on a semiconductor substrate.
On the layout shown in the top view of FIG. 9B, a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, and a fourth gate electrode G4 are formed to cross each of corresponding semiconductor areas described above. In addition, on each surface of semiconductor areas excluding each area for forming each gate electrode, source and drain areas are formed to form each of the first and second load transistors LTr1 and LTr2 each serving as PMOS transistor, the first and second driver transistors DTr1 and DTr2 each serving as NMOS transistors, and the first and second transfer transistors TTr1 and TTr2 each serving as NMOS transistors.
An opening is formed to start continuously from the source and drain area of the first load transistor LTr1 formed to operate as a PMOS transistor to an area covering the third gate electrode G3, and a common contact SCT1 is provided in the opening to connect the source and drain area of the first load transistor LTr1 to the third gate electrode G3.
On the other hand, an opening is formed in the source and drain area connecting the first driver transistor DTr1 to the first transfer transistor TTr1, and a contact CT1 is provided in the opening. The contact CT1 is connected to the common contact SCT1 by an upper-layer wire (not shown in FIG. 9B) to form the first storage node ND in the equivalent circuit shown in the circuit diagram of FIG. 9A.
By the same token, an opening is formed to start continuously from the source and drain area of the second load transistor LTr2 formed to operate as a PMOS transistor to an area covering the first gate electrode G1, and a common contact SCT2 is provided in the opening to connect the source and drain area of the second load transistor LTr2 to the first gate electrode G1.
On the other hand, an opening is formed in the source and drain area connecting the second driver transistor DTr2 to the second transfer transistor TTr2, and a contact CT2 is provided in the opening.
In the same way as the contact CT1 is connected to the common contact SCT1 as described above, the contact CT2 is connected to the common contact SCT2 by an upper-layer wire (not shown in FIG. 9B) to form the second storage node ND/ in the equivalent circuit shown in the circuit diagram of FIG. 9A.
The source and drain areas are connected to upper-layer wires through their respective contacts in order to wire the source and drain areas to the power-supply voltage Vc, the reference electric potential Vs, the bit line BL and the complementary-bit line BL/.
The components connected to each other as described above form a memory cell MC.
In the SRAM having the configuration described above, each memory cell MC employs NMOS and PMOS transistors. With the area of the memory cell MC contracted, the gaps between the NMOS and PMOS transistors become narrow too. That is to say, the gaps between the first P-type semiconductor area P1, the second P-type semiconductor area P2, the first N-type semiconductor area N1 and the second N-type semiconductor area N2 which are formed on the semiconductor substrate become narrow.
The following description explains a method of manufacturing an SRAM employing memory cells MC each having the configuration described above.
FIG. 10A is a top view of first N-type semiconductor areas N1 and N3, second N-type semiconductor areas N2 and N4, first P-type semiconductor areas P1 and P3 as well as second P-type semiconductor areas P2 and P4 in a process to form each of the areas as a well on a semiconductor substrate 10 by adoption of the method. On the other hand, FIG. 10B is a cross-sectional diagram showing a model of the cross section of the semiconductor areas shown in the top view of FIG. 10A.
Each of the diagrams of FIGS. 10A and 10B shows two memory cells MC1 and MC2 which are adjacent to each other. The area of the memory cell MC1 includes the first P-type semiconductor area P1 for NMOS transistors, the second P-type semiconductor area P2 for NMOS transistors, the first N-type semiconductor area N1 for a PMOS transistor and the second N-type semiconductor area N2 for a PMOS transistor. By the same token, the area of the memory cell MC2 includes the first P-type semiconductor area P3 for NMOS transistors, the second P-type semiconductor area P4 for NMOS transistors, the first N-type semiconductor area N3 for a PMOS transistor and the second N-type semiconductor area N4 for a PMOS transistor.
First of all, a device separating isolation film I is formed on the semiconductor substrate 10 to separate active area segments from each other as shown in FIG. 10B. Then, each of areas allocated to the first P-type semiconductor areas P1 and P3 as well as the second P-type semiconductor areas P2 and P4 is protected by a mask such as a resist film. Subsequently, ions each serving as an impurity of n-type conductivity are injected in an ion injection process to form the first N-type semiconductor areas N1 and N3 as well as the second N-type semiconductor areas N2 and N4.
Then, each of the first N-type semiconductor areas N1 and N3 as well as the second N-type semiconductor areas N2 and N4 is protected by a mask MK such as a resist film as shown in FIGS. 10A and 10B. Subsequently, ions each serving as an impurity of p-type conductivity are injected to form the first P-type semiconductor areas P1 and P3 as well as the second P-type semiconductor areas P2 and P4.
Ions each serving as a conductive impurity are injected in the above process in a direction forming an angle relative to the surface of the semiconductor substrate 10.
Let us think of a case in which the creation positions of the formed masks MK for protecting the first N-type semiconductor areas N1 and N3 as well as the second N-type semiconductor areas N2 and N4 are inadvertently shifted in the process of forming the first P-type semiconductor areas P1 and P3 as well as the second P-type semiconductor areas P2 and P4.
FIG. 11A is a top view of the first P-type semiconductor areas P1 and P3 as well as the second P-type semiconductor areas P2 and P4 in a process to form each of the first P-type semiconductor areas P1 and P3 as well as the second P-type semiconductor areas P2 and P4 on the semiconductor substrate 10 as a well. The creation position of each of the masks MK is undesirably shifted from its supposed position MK0 to the right direction in the top view of FIG. 11A. FIG. 11B is a top view showing a relation between the layout patterns of the memory cells MC1 and MC2 adjacent to each other.
As shown in the top view of FIG. 11A, in the memory cell MC1, the mask MK is moved to a position farther from the first P-type semiconductor area P1 but closer to the second P-type semiconductor area P2 than the supposed mask position MK0.
In the memory cell MC2, on the other hand, the mask MK is moved to a position farther from the second P-type semiconductor area P4 but closer to the first P-type semiconductor area P3 than the supposed mask position MK0. This is because, for the purpose of allowing contacts to be shared by the memory cells MC1 and MC2 and other purposes, the layout patterns of the memory cells MC1 and MC2 are deliberately made symmetrical in the horizontal direction with respect to the center vertical line or the layout patterns of the memory cells MC1 and MC2 are deliberately made opposite to each other in the horizontal direction as shown in the top view of FIG. 11B.
FIG. 12 is a model cross-sectional diagram referred to in description of problems raised by the hitherto known technology. An NMOS area ANMOS shown in the model cross-sectional diagram of FIG. 12 is an enlarged figure of a P-type semiconductor area shown in the diagrams of FIGS. 10A to 11B as a semiconductor area for forming NMOS transistors. On the other hand, a PMOS area APMOS shown in the model cross-sectional diagram of FIG. 12 is an enlarged figure of an N-type semiconductor area shown in the diagrams of FIGS. 10A to 11B as a semiconductor area for forming a PMOS transistor.
In the model cross-sectional diagram of FIG. 12, the NMOS area ANMOS is the second P-type semiconductor area P2. With a mask MK placed at a location close to the second P-type semiconductor area P2 as shown in the model cross-sectional diagram of FIG. 12, due to an inclined ion injection direction denoted by notation II, a shadow is cast by the mask MK on an area SH, resulting in inadequate ion injection onto the area SH.
As a result, in a transistor with conductive impurities not injected thereto at a design concentration in an ion injection process, the characteristic of the transistor is not fixed. Since conductive impurities are not injected into the first P-type semiconductor area P1 of the memory cell MC1 at a design concentration in an ion injection process, the characteristic of each of the first driver transistor DTr1 and the first transfer transistor TTr1 is not fixed inadvertently. By the same token, since conductive impurities are not injected into the second P-type semiconductor area P2 of the memory cell MC1 at a design concentration in an ion injection process, the characteristic of each of the second driver transistor DTr2 and the second transfer transistor TTr2 is also not fixed inadvertently either.
If the characteristic undesirably varies much from transistor to transistor in the same memory cell MC as described above, the characteristics of the SRAM deteriorate. The characteristics of the SRAM include a characteristic to write data into memory cell MC in the SRAM, a characteristic to hold the written data in the memory cell MC and a characteristic to read out the data held in the memory cell MC from the memory cell MC.
As described above, the layout patterns of the memory cells MC1 and MC2 are deliberately made symmetrical in the horizontal direction with respect to the center vertical line or the layout patterns of the memory cells MC1 and MC2 are deliberately made opposite to each other in the horizontal direction as shown in the top view of FIG. 11B. Thus, the creation position of the mask MK on the memory cell MC1 is shifted in a direction opposite to the direction in which the mask MK on the memory cell MC2 is shifted. As a result, the characteristics of the memory cell MC1 are shifted in a direction opposite to the direction in which the characteristics of the memory cell MC2 are shifted. That is, the characteristics of a memory cell MC vary from cell to cell so that the characteristics of the SRAM deteriorate as described above.
Unlike what has been described above, Japanese Patent Laid-open No. 2000-31298 (patent document 1) discloses a layout in which the first transfer transistor TTr1, the first driver transistor DTr1, the second driver transistor DTr2 and the second transfer transistor TTr2, which compose a memory cell MC of an SRAM, are connected in series and aligned to form a straight line.
In the layout disclosed in patent document 1, for the purpose of allowing contacts to be shared, it is natural to deliberately make the layout patterns of the memory cells MC1 and MC2 symmetrical in the horizontal direction with respect to the center vertical line or deliberately make the layout patterns of the memory cells MC1 and MC2 opposite to each other in the horizontal direction. Thus, if the creation positions of the masks MK are shifted, the characteristics of a memory cell MC vary from cell to cell so that the characteristics of the SRAM deteriorate.